1. Field of Invention
The present invention relates to the field of electronics, and, more particularly, to the field of signal processing devices and methods for wireless communication.
2. Description of Prior Art
Analog-to-digital converter performance is limited by trade-offs between sampling rate and resolution in bits. Within the sampling rate range of approximately 1 million to 1 billion samples per second, these trade-offs are imposed firstly by timing jitter in the sampling process and secondarily by thermal noise in the sampling process. Prior art analog-to-digital converter designs, including time-interleaved designs, all suffer from the same limitations because they must take precisely timed short samples of the analog signal to be converted in order to provide precise, and therefore, high spurious-free dynamic range (SFDR) and high signal-to-noise ratio (SNR) conversion. Digital-to-analog converters are also subject to these limitations but are less severely impacted due to typically less strenuous SFDR and SNR requirements. In prior art, high-resolution, high sampling rate conversion also requires the sampling time of the analog signal to be short and therefore subject to thermal noise associated with the small amount of energy available from the signal in each sample. These limits on prior analog-to-digital conversion technology were recently described in Robert H. Walden, xe2x80x9cPerformance Trends for Analog-to-Digital Converters,xe2x80x9d IEEE Communications Magazine, 96-101, February 1999. Walden points out that progress in improving the sample rate to bit resolution trade-off has been slow, yielding only about 1.5 bits improvement over the previous eight years.
Time-interleaved converters use parallelism to reduce the sample rate required of each converter element in a parallel array. This arrangement does not reduce timing jitter for any particular sample and therefore does not improve the SNR. However, the clock skew between the parallel elements which impacts the SFDR can be improved somewhat through interpolation between the parallel elements. This is described in: Huawen Jin and Edward K. F. Lee, xe2x80x9cA Digital-Background Calibration Technique for Minimizing Timing-Error Effects in Time-Interleaved ADC""s,xe2x80x9d IEEE Transactions on Circuits and Systemsxe2x80x94II: Analog and Digital Signal Processing, 41(7):603-613 (July, 2000).
Velazquez et al., U.S. Pat. No. 5,568,142, describes a hybrid filter bank analog-to-digital and digital-to-analog converter, which decomposes the analog signal into frequency sub-bands. This is similar to a wavelet decomposition into time and frequency bins. While this approach provides a means to increase bit resolution and compensate for nonlinearities, it lacks the ability to maintain precise synchronization between frequency subbands in the range of 1 million to 1 billion samples per second.
Edwards et al., U.S. Pat. No. 5,495,554, describes an analog circuit to generate a wavelet decomposition of a signal. This circuit has the advantage of being much smaller and much less power consuming than its digital counterpart. However, it also lacks the ability to maintain precise synchronization in the range of 1 million to 1 billion samples per second.
The present invention provides a means for direct intermediate frequency sampling analog-to-digital and digital-to-analog signal conversion at combinations of sampling rates and bit resolutions previously not possible. This results in a combination of high sample rate, high SNR and high SFDR direct intermediate frequency sampling analog-to-digital and digital-to-analog conversion providing high sample rate and high bit resolution conversion not attainable with prior art.
The present invention overcomes the bandwidth, SNR, and SFDR limitations of prior art analog-to-digital and digital-to-analog converter technology by decomposing or composing the analog signal into a set of wavelet functions rather than sampling it in the time domain. This wavelet decomposition allows for the detection and correction of extremely small timing errors and thus overcomes the timing jitter limitations of existing analog-to-digital converter technology. In addition, the wavelet decomposition integrates signal energy over much longer periods than the time domain sampling. As a result, each element of the wavelet-decomposed signal contains much more energy than each sample in a time domain sampling approach and therefore is much less affected by thermal noise. Also, the particular wavelet function, used to provide direct intermediate frequency sampling response in the present embodiment, greatly simplifies the required circuitry compared with the basic wavelet-based analog-to-digital and digital-to-analog converter concept of my co-pending application Ser. No. 09/669,693. Further objects and advantages may become apparent from consideration of the drawings and ensuing description.